更新硬件SDK

2025-12-21 02:15:55 +08:00 · 2023-03-04 03:44:56 +08:00
parent dcdf6e1b7c
commit e39d3d2f03
1900 changed files with 663153 additions and 0 deletions
--- a/sdk/合宙/air780e/csdk/luatos-soc-2022/project/example_gpio/inc/RTE_Device.h
+++ b/sdk/合宙/air780e/csdk/luatos-soc-2022/project/example_gpio/inc/RTE_Device.h
@@ -0,0 +1,350 @@
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+#include "ec618.h"
+
+/*  Peripheral IO Mode Select, Must Configure First !!!
+    Note, when receiver works in DMA_MODE, interrupt is also enabled to transfer tailing bytes.
+*/
+
+#define POLLING_MODE            0x1
+#define DMA_MODE                0x2
+#define IRQ_MODE                0x3
+#define UNILOG_MODE             0x4
+
+#define RTE_UART0_TX_IO_MODE    UNILOG_MODE
+#define RTE_UART0_RX_IO_MODE    IRQ_MODE
+#define USART0_RX_TRIG_LVL      (30)
+
+#define RTE_UART1_TX_IO_MODE    DMA_MODE
+#define RTE_UART1_RX_IO_MODE    DMA_MODE
+
+#define RTE_UART2_TX_IO_MODE    POLLING_MODE
+#define RTE_UART2_RX_IO_MODE    DMA_MODE
+
+#define RTE_SPI0_IO_MODE        POLLING_MODE
+
+#define RTE_SPI1_IO_MODE        POLLING_MODE
+
+#define RTE_I2C0_IO_MODE        POLLING_MODE
+#define RTE_I2C1_IO_MODE        POLLING_MODE
+
+
+// I2C0 (Inter-integrated Circuit Interface) [Driver_I2C0]
+// Configuration settings for Driver_I2C0 in component ::Drivers:I2C
+#define RTE_I2C0                        1
+
+// { PAD_PIN28},  // 0 : gpio13 / 2 : I2C0 SCL
+// { PAD_PIN27},  // 0 : gpio12 / 2 : I2C0 SDA
+#define RTE_I2C0_SCL_BIT                28			// AUDIO use 28
+#define RTE_I2C0_SCL_FUNC               PAD_MUX_ALT2
+
+#define RTE_I2C0_SDA_BIT                27			// AUDIO use 27
+#define RTE_I2C0_SDA_FUNC               PAD_MUX_ALT2
+
+// DMA
+//   Tx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_I2C0_DMA_TX_EN              0
+#define RTE_I2C0_DMA_TX_REQID           DMA_REQUEST_I2C0_TX
+//   Rx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_I2C0_DMA_RX_EN              0
+#define RTE_I2C0_DMA_RX_REQID           DMA_REQUEST_I2C0_RX
+
+// I2C1 (Inter-integrated Circuit Interface) [Driver_I2C1]
+// Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+#define RTE_I2C1                        1
+
+// { PAD_PIN20},  // 0 : gpio5  / 2 : I2C1 SCL
+// { PAD_PIN19},  // 0 : gpio4  / 2 : I2C1 SDA
+#define RTE_I2C1_SCL_BIT                20
+#define RTE_I2C1_SCL_FUNC               PAD_MUX_ALT2
+
+#define RTE_I2C1_SDA_BIT                19
+#define RTE_I2C1_SDA_FUNC               PAD_MUX_ALT2
+
+// DMA
+//   Tx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_I2C1_DMA_TX_EN              1
+#define RTE_I2C1_DMA_TX_REQID           DMA_REQUEST_I2C1_TX
+//   Rx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_I2C1_DMA_RX_EN              1
+#define RTE_I2C1_DMA_RX_REQID           DMA_REQUEST_I2C1_RX
+
+
+// UART0 (Universal asynchronous receiver transmitter) [Driver_USART0]
+// Configuration settings for Driver_USART0 in component ::Drivers:USART
+#define RTE_UART0_CTS_PIN_EN            0
+#define RTE_UART0_RTS_PIN_EN            0
+
+// { PAD_PIN27},  // 0 : gpio12 / 3 : UART0 RTSn
+// { PAD_PIN28},  // 0 : gpio13 / 3 : UART0 CTSn
+// { PAD_PIN29},  // 0 : gpio14 / 3 : UART0 RXD
+// { PAD_PIN30},  // 0 : gpio15 / 3 : UART0 TXD
+#define RTE_UART0_RTS_BIT               27
+#define RTE_UART0_RTS_FUNC              PAD_MUX_ALT3
+
+#define RTE_UART0_CTS_BIT               28
+#define RTE_UART0_CTS_FUNC              PAD_MUX_ALT3
+
+#define RTE_UART0_RX_BIT                29
+#define RTE_UART0_RX_FUNC               PAD_MUX_ALT3
+
+#define RTE_UART0_TX_BIT                30
+#define RTE_UART0_TX_FUNC               PAD_MUX_ALT3
+
+// DMA
+//  Tx
+//    Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_UART0_DMA_TX_REQID          DMA_REQUEST_USART0_TX
+//  Rx
+//    Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_UART0_DMA_RX_REQID          DMA_REQUEST_USART0_RX
+
+// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
+// Configuration settings for Driver_USART1 in component ::Drivers:USART
+#define RTE_UART1_CTS_PIN_EN            1
+#define RTE_UART1_RTS_PIN_EN            1
+
+// { PAD_PIN31},  // 0 : gpio16  / 1 : UART1 RTS
+// { PAD_PIN32},  // 0 : gpio17  / 1 : UART1 CTS
+// { PAD_PIN33},  // 0 : gpio18  / 1 : UART1 RXD
+// { PAD_PIN34},  // 0 : gpio19  / 1 : UART1 TXD
+#define RTE_UART1_RTS_BIT               31
+#define RTE_UART1_RTS_FUNC              PAD_MUX_ALT1
+
+#define RTE_UART1_CTS_BIT               32
+#define RTE_UART1_CTS_FUNC              PAD_MUX_ALT1
+
+#define RTE_UART1_RX_BIT                33
+#define RTE_UART1_RX_FUNC               PAD_MUX_ALT1
+
+#define RTE_UART1_TX_BIT                34
+#define RTE_UART1_TX_FUNC               PAD_MUX_ALT1
+
+// DMA
+//   Tx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_UART1_DMA_TX_REQID          DMA_REQUEST_USART1_TX
+//   Rx
+//     Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_UART1_DMA_RX_REQID          DMA_REQUEST_USART1_RX
+
+// UART2 (Universal asynchronous receiver transmitter) [Driver_USART2]
+// Configuration settings for Driver_USART2 in component ::Drivers:USART
+#define RTE_UART2_CTS_PIN_EN            0
+#define RTE_UART2_RTS_PIN_EN            0
+
+// { PAD_PIN25},  // 0 : gpio10 / 3 : UART2 RXD
+// { PAD_PIN26},  // 0 : gpio11 / 3 : UART2 TXD
+#define RTE_UART2_RX_BIT                25
+#define RTE_UART2_RX_FUNC               PAD_MUX_ALT3
+
+#define RTE_UART2_TX_BIT                26
+#define RTE_UART2_TX_FUNC               PAD_MUX_ALT3
+
+
+// DMA
+//   Tx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_UART2_DMA_TX_REQID          DMA_REQUEST_USART2_TX
+//   Rx
+//     Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_UART2_DMA_RX_REQID          DMA_REQUEST_USART2_RX
+
+// SPI0 (Serial Peripheral Interface) [Driver_SPI0]
+// Configuration settings for Driver_SPI0 in component ::Drivers:SPI
+#define RTE_SPI0                        1
+
+// { PAD_PIN21},  // 0 : gpio16 / 1 : UART1 RTS / 2 : SPI0 SSn
+// { PAD_PIN22},  // 0 : gpio11 / 1 : UART1 CTS / 2 : SPI0 MOSI
+// { PAD_PIN23},  // 0 : gpio14 / 1 : UART1 RXD / 2 : SPI0 MISO
+// { PAD_PIN24},  // 0 : gpio15 / 1 : UART1 TXD / 2 : SPI0 SCLK
+#define RTE_SPI0_SSN_BIT                21
+#define RTE_SPI0_SSN_FUNC               PAD_MUX_ALT2
+
+#define RTE_SPI0_MOSI_BIT               22
+#define RTE_SPI0_MOSI_FUNC              PAD_MUX_ALT2
+
+#define RTE_SPI0_MISO_BIT               23
+#define RTE_SPI0_MISO_FUNC              PAD_MUX_ALT2
+
+#define RTE_SPI0_SCLK_BIT               24
+#define RTE_SPI0_SCLK_FUNC              PAD_MUX_ALT2
+
+#define RTE_SPI0_SSN_GPIO_INSTANCE      1
+#define RTE_SPI0_SSN_GPIO_INDEX         0
+
+// DMA
+//   Tx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_SPI0_DMA_TX_REQID           DMA_REQUEST_SPI0_TX
+
+//   Rx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_SPI0_DMA_RX_REQID           DMA_REQUEST_SPI0_RX
+
+// SPI1 (Serial Peripheral Interface) [Driver_SPI1]
+// Configuration settings for Driver_SPI1 in component ::Drivers:SPI
+#define RTE_SPI1                        1
+
+// { PAD_PIN13},  // 0 : gpio2 / 1 : UART0 RTSn / 3 : SPI1 SSn
+// { PAD_PIN14},  // 0 : gpio3 / 1 : UART0 CTSn / 3 : SPI1 MOSI
+// { PAD_PIN15},  // 0 : gpio4 / 1 : UART0 RXD  / 3 : SPI1 MISO
+// { PAD_PIN16},  // 0 : gpio5 / 1 : UART0 TXD  / 3 : SPI1 SCLK
+#define RTE_SPI1_SSN_BIT                13
+#define RTE_SPI1_SSN_FUNC               PAD_MUX_ALT3
+
+#define RTE_SPI1_MOSI_BIT               14
+#define RTE_SPI1_MOSI_FUNC              PAD_MUX_ALT3
+
+#define RTE_SPI1_MISO_BIT               15
+#define RTE_SPI1_MISO_FUNC              PAD_MUX_ALT3
+
+#define RTE_SPI1_SCLK_BIT               16
+#define RTE_SPI1_SCLK_FUNC              PAD_MUX_ALT3
+
+#define RTE_SPI1_SSN_GPIO_INSTANCE      0
+#define RTE_SPI1_SSN_GPIO_INDEX         2
+
+// DMA
+//   Tx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_SPI1_DMA_TX_REQID           DMA_REQUEST_SPI1_TX
+
+//   Rx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_SPI1_DMA_RX_REQID           DMA_REQUEST_SPI1_RX
+
+
+// PWM0 Controller [Driver_PWM0]
+// Configuration settings for Driver_PWM0 in component ::Drivers:PWM
+#define RTE_PWM                         1
+
+#define EFUSE_INIT_MODE POLLING_MODE
+#define L2CTLS_INIT_MODE POLLING_MODE
+
+#define FLASH_BARE_RW_MODE 1
+
+
+
+
+
+#define RTE_UART0                       1
+#define RTE_UART1                       1
+#define RTE_UART2                       1
+/* to enable external thermal */
+#define EXTERNAL_NTC_EXIST              0
+
+
+#if (RTE_UART1 == 1)
+#define UART1_DTR_PAD_INDEX             26     // GPIO11
+#define UART1_DTR_GPIO_INSTANCE         0
+#define UART1_DTR_GPIO_PIN              11
+
+#define UART1_RI_PAD_INDEX              44     // AONIO 4 = GPIO24
+#define UART1_RI_GPIO_INSTANCE          1
+#define UART1_RI_GPIO_PIN               8
+#define UART1_RI_PWM_INSTANCE           1
+#define UART1_RI_PWM_CLK_ID             FCLK_TIMER1
+#define UART1_RI_PWM_CLK_SEL            FCLK_TIMER1_SEL_26M
+
+#define UART1_DCD_PAD_INDEX             45     // AONIO 5 = GPIO25
+#define UART1_DCD_GPIO_INSTANCE         1
+#define UART1_DCD_GPIO_PIN              9
+#endif
+
+#if (RTE_UART2 == 1)
+#define UART2_DTR_PAD_INDEX             25     // GPIO10
+#define UART2_DTR_GPIO_INSTANCE         0
+#define UART2_DTR_GPIO_PIN              10
+
+#define UART2_RI_PAD_INDEX              43     // AONIO 3 = GPIO23
+#define UART2_RI_GPIO_INSTANCE          1
+#define UART2_RI_GPIO_PIN               7
+#define UART2_RI_PWM_INSTANCE           0
+#define UART2_RI_PWM_CLK_ID             FCLK_TIMER0
+#define UART2_RI_PWM_CLK_SEL            FCLK_TIMER0_SEL_26M
+
+#define UART2_DCD_PAD_INDEX             47     // AONIO 7 = GPIO27
+#define UART2_DCD_GPIO_INSTANCE         1
+#define UART2_DCD_GPIO_PIN              11
+#endif
+
+
+#define NETLIGHT_PAD_INDEX              46     // AONIO 6 = GPIO26
+#define NETLIGHT_PAD_ALT_FUNC           PAD_MUX_ALT5
+#define NETLIGHT_PWM_INSTANCE           3
+
+//USIM1 OPTION1
+#define USIM1_URST_OP1_PAD_INDEX             19     // GPIO4
+#define USIM1_URST_OP1_GPIO_INSTANCE         0
+#define USIM1_URST_OP1_GPIO_PIN              4
+#define USIM1_UCLK_OP1_PAD_INDEX             20     // GPIO5
+#define USIM1_UCLK_OP1_GPIO_INSTANCE         0
+#define USIM1_UCLK_OP1_GPIO_PIN              5
+#define USIM1_UIO_OP1_PAD_INDEX              21     // GPIO6
+#define USIM1_UIO_OP1_GPIO_INSTANCE          0
+#define USIM1_UIO_OP1_GPIO_PIN               6
+
+//USIM1 OPTION2
+#define USIM1_UIO_OP2_PAD_INDEX              27     // GPIO12
+#define USIM1_UIO_OP2_GPIO_INSTANCE          0
+#define USIM1_UIO_OP2_GPIO_PIN               12
+#define USIM1_URST_OP2_PAD_INDEX             28     // GPIO13
+#define USIM1_URST_OP2_GPIO_INSTANCE         0
+#define USIM1_URST_OP2_GPIO_PIN              13
+#define USIM1_UCLK_OP2_PAD_INDEX             29     // GPIO14
+#define USIM1_UCLK_OP2_GPIO_INSTANCE         0
+#define USIM1_UCLK_OP2_GPIO_PIN              14
+
+//USIM1 clock latched by AONIO, for example, use AONIO-6 test on EVB
+#define AONIO_6_PAD_INDEX        46     // AONIO 6 = GPIO26
+#define AONIO_6_GPIO_INSTANCE    1
+#define AONIO_6_GPIO_PIN         10
+
+#define RTE_CSPI0                       0
+
+#define RTE_CSPI0_MCLK_PAD_ADDR         39
+#define RTE_CSPI0_MCLK_FUNC             PAD_MUX_ALT1
+
+#define RTE_CSPI0_PCLK_PAD_ADDR         35
+#define RTE_CSPI0_PCLK_FUNC             PAD_MUX_ALT1
+
+#define RTE_CSPI0_CS_PAD_ADDR           36
+#define RTE_CSPI0_CS_FUNC               PAD_MUX_ALT1
+
+#define RTE_CSPI0_SDO0_PAD_ADDR         37
+#define RTE_CSPI0_SDO0_FUNC             PAD_MUX_ALT1
+
+#define RTE_CSPI0_SDO1_PAD_ADDR         38
+#define RTE_CSPI0_SDO1_FUNC             PAD_MUX_ALT1
+
+// DMA CSPI0 Request ID
+#define RTE_CSPI0_DMA_RX_REQID          DMA_REQUEST_I2S0_RX
+
+// CSPI1 Configuration
+#define RTE_CSPI1                       1
+
+#define RTE_CSPI1_MCLK_PAD_ADDR         18
+#define RTE_CSPI1_MCLK_FUNC             PAD_MUX_ALT1
+
+#define RTE_CSPI1_PCLK_PAD_ADDR         19
+#define RTE_CSPI1_PCLK_FUNC             PAD_MUX_ALT1
+
+#define RTE_CSPI1_CS_PAD_ADDR           20
+#define RTE_CSPI1_CS_FUNC               PAD_MUX_ALT1
+
+#define RTE_CSPI1_SDO0_PAD_ADDR         21
+#define RTE_CSPI1_SDO0_FUNC             PAD_MUX_ALT1
+
+#define RTE_CSPI1_SDO1_PAD_ADDR         22
+#define RTE_CSPI1_SDO1_FUNC             PAD_MUX_ALT1
+
+// DMA CSPI1 Request ID
+#define RTE_CSPI1_DMA_RX_REQID          DMA_REQUEST_I2S1_RX
+
+#endif  /* __RTE_DEVICE_H */
--- a/sdk/合宙/air780e/csdk/luatos-soc-2022/project/example_gpio/src/example_gpio.c
+++ b/sdk/合宙/air780e/csdk/luatos-soc-2022/project/example_gpio/src/example_gpio.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2022 OpenLuat & AirM2M
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "common_api.h"
+#include "luat_rtos.h"
+#include "luat_debug.h"
+#include "luat_gpio.h"
+#include "platform_define.h"
+
+/*
+移芯618平台上GPIO使用有如下注意事项：
+
+系统有几种工作模式：ACTIVE、IDLE、SLEEP1、SLEEP2、HIBERNATE，几种模式的区别，参考example_pm的说明；
+
+1、IO分为normal IO和retention/AON IO两种
+   normal IO：普通IO
+              在ACTIVE和IDLE工作模式下，可以正常控制使用；
+			  在SLEEP1、SLEEP2、HIBERNATE工作模式下，IO电源被强制关闭，无法使用；
+   retention/AON IO：保持IO
+              在ACTIVE和IDLE工作模式下，可以正常控制使用；
+			  在SLEEP1、SLEEP2、HIBERNATE工作模式下，只能作为输出使用，而且只能维持一种输出电平状态，无法翻转控制；
+
+2、带AON功能的引脚，做retention/AON IO功能或者其他外设功能使用时，做软件配置上拉无效，只能使用默认的上下拉；
+
+3、系统进入SLEEP1、SLEEP2、HIBERNATE休眠模式后，除了软件运行代码调用唤醒接口可以主动唤醒外，可以唤醒的外部事件有以下几种：
+   (1). 配置为wakeup软件功能的wakeup pad引脚；
+   (2). low power uart，如果波特率为9600，唤醒时数据也不会丢失，其他波特率会丢失前面的部分数据；
+   (3). low power usb
+   (4). power key；
+   (5). charge pad；
+   (6). rtc；
+   详情参考example_pm的说明。
+
+4、所有IO都支持中断：
+   GPIO20、GPIO21、GPIO22三个IO支持同时配置为双边沿中断或者同时配置为高低电平中断；
+
+   其余GPIO仅支持单边沿、单电平中断；如果这些GPIO配置了双边沿或者双电平中断，则会被系统自动调整配置为上升沿或者高电平中断；
+   所以为了防止被系统自动调整配置，其余的这些GPIO，使用中断时仅配置为单边沿或者单电平中断。
+*/
+
+//本example基于EVB_Air780E_V1.5硬件
+
+#define NET_LED_PIN HAL_GPIO_27
+#define LCD_RST_PIN HAL_GPIO_1
+
+#define LCD_RS_PIN HAL_GPIO_10
+#define LCD_CS_PIN HAL_GPIO_8
+
+#define DTR_PIN HAL_GPIO_22
+#define LCD_DATA_PIN HAL_GPIO_9
+
+#define DEMO_IRQ_PIN HAL_GPIO_20
+
+//控制NET指示灯闪烁
+static void task_gpio_output_run(void *param)
+{	
+	luat_gpio_cfg_t gpio_cfg;
+	luat_gpio_set_default_cfg(&gpio_cfg);
+
+	gpio_cfg.pin = NET_LED_PIN;
+	luat_gpio_open(&gpio_cfg);
+	while(1)
+	{
+		luat_gpio_set(NET_LED_PIN, 1);
+		LUAT_DEBUG_PRINT("net led on");
+		luat_rtos_task_sleep(1000);
+		luat_gpio_set(NET_LED_PIN, 0);
+		LUAT_DEBUG_PRINT("net led off");
+		luat_rtos_task_sleep(1000);
+	}	
+}
+
+void task_gpio_output_init(void)
+{
+	luat_rtos_task_handle task_gpio_output_handle;
+	luat_rtos_task_create(&task_gpio_output_handle, 4 * 1204, 50, "gpio_output_test", task_gpio_output_run, NULL, 32);
+}
+
+
+//LCD_RST引脚和NET引脚短接
+//NET引脚：通过task_gpio_output_run函数每隔一秒翻转一次输出高低电平
+//LCD_RST引脚：每隔一秒读取一次输入电平
+void task_gpio_input_run(void)
+{
+	luat_gpio_cfg_t gpio_cfg;
+	luat_gpio_set_default_cfg(&gpio_cfg);
+
+	gpio_cfg.pin = LCD_RST_PIN;
+	gpio_cfg.mode = LUAT_GPIO_INPUT;
+	luat_gpio_open(&gpio_cfg);
+
+	int level = 0;
+
+	while(1)
+	{
+		level = luat_gpio_get(LCD_RST_PIN);
+		LUAT_DEBUG_PRINT("get lcd rst pin %d",level);
+		luat_rtos_task_sleep(1000);
+		level = luat_gpio_get(LCD_RST_PIN);
+		LUAT_DEBUG_PRINT("get lcd rst pin %d",level);
+		luat_rtos_task_sleep(1000);
+	}
+}
+
+void task_gpio_input_init(void)
+{
+	luat_rtos_task_handle task_gpio_input_handle;
+	luat_rtos_task_create(&task_gpio_input_handle, 4 * 1204, 50, "gpio_input_test", task_gpio_input_run, NULL, 32);
+}
+
+int single_interrupt_cnt = 0;
+int both_interrupt_cnt = 0;
+int gpio_irq(int pin, void* args)
+{
+	if (pin == LCD_CS_PIN)
+	{
+		single_interrupt_cnt++;
+	}
+	else if (pin == DTR_PIN)
+	{
+		both_interrupt_cnt++;
+	}	
+	
+	//注意：中断服务程序中的一行LUAT_DEBUG_PRINT日志，如果通过Luatools查看，最多仅支持64字节
+	LUAT_DEBUG_PRINT("pin:%d, level:%d,", pin, luat_gpio_get(pin));
+}
+
+//GPIO单边沿中断测试
+void task_gpio_single_interrupt_run(void)
+{
+	luat_gpio_cfg_t gpio_cfg;
+
+	//配置LCD_CS_PIN为中断引脚
+	luat_gpio_set_default_cfg(&gpio_cfg);
+	gpio_cfg.pin = LCD_CS_PIN;
+	gpio_cfg.mode = LUAT_GPIO_IRQ;
+
+	//LCD_CS_PIN引脚仅支持单边沿或者单电平类型的中断；
+	//此处仅演示单边沿中断，配置为LUAT_GPIO_RISING_IRQ、LUAT_GPIO_FALLING_IRQ
+	//不要配置为LUAT_GPIO_BOTH_IRQ，因为配置为LUAT_GPIO_BOTH_IRQ会被系统自动修改为LUAT_GPIO_RISING_IRQ；
+	gpio_cfg.irq_type = LUAT_GPIO_RISING_IRQ; 
+
+	gpio_cfg.pull = LUAT_GPIO_PULLUP;
+	gpio_cfg.irq_cb = gpio_irq;	
+	luat_gpio_open(&gpio_cfg);
+
+	//配置LCD_RS_PIN为输出引脚
+	luat_gpio_set_default_cfg(&gpio_cfg);
+	gpio_cfg.pin = LCD_RS_PIN;
+	luat_gpio_open(&gpio_cfg);
+
+	while(1)
+	{
+		luat_gpio_set(LCD_RS_PIN, 1);
+		LUAT_DEBUG_PRINT("LCD_RS output %d, LCD_CS input %d",luat_gpio_get(LCD_RS_PIN), luat_gpio_get(LCD_CS_PIN));
+		luat_rtos_task_sleep(1000);
+		LUAT_DEBUG_PRINT("after high input, number of single interrupts %d", single_interrupt_cnt);
+
+		luat_gpio_set(LCD_RS_PIN, 0);
+		LUAT_DEBUG_PRINT("LCD_RS output %d, LCD_CS input %d",luat_gpio_get(LCD_RS_PIN), luat_gpio_get(LCD_CS_PIN));
+		luat_rtos_task_sleep(1000);
+		LUAT_DEBUG_PRINT("after low input, number of single interrupts %d", single_interrupt_cnt);		
+	}	
+
+}
+
+void task_gpio_single_interrupt_init(void)
+{
+	luat_rtos_task_handle task_gpio_single_interrupt_handle;
+	luat_rtos_task_create(&task_gpio_single_interrupt_handle, 4 * 1204, 50, "gpio_single_interrupt_test", task_gpio_single_interrupt_run, NULL, 32);
+}
+
+
+//GPIO双边沿中断测试
+void task_gpio_both_interrupt_run(void)
+{
+	luat_gpio_cfg_t gpio_cfg;
+
+	//配置DTR为中断引脚
+	luat_gpio_set_default_cfg(&gpio_cfg);
+	gpio_cfg.pin = DTR_PIN;
+	gpio_cfg.mode = LUAT_GPIO_IRQ;
+
+	//DTR_PIN引脚支持双边沿或者高低电平类型的中断；
+	//此处仅演示双边沿中断，可以配置为LUAT_GPIO_BOTH_IRQ、LUAT_GPIO_RISING_IRQ、LUAT_GPIO_FALLING_IRQ
+	gpio_cfg.irq_type = LUAT_GPIO_BOTH_IRQ; 
+
+	gpio_cfg.pull = LUAT_GPIO_PULLUP;
+	gpio_cfg.irq_cb = gpio_irq;	
+	luat_gpio_open(&gpio_cfg);
+
+	//配置LCD_DATA_PIN为输出引脚
+	luat_gpio_set_default_cfg(&gpio_cfg);
+	gpio_cfg.pin = LCD_DATA_PIN;
+	luat_gpio_open(&gpio_cfg);
+
+	while(1)
+	{
+		luat_gpio_set(LCD_DATA_PIN, 1);
+		LUAT_DEBUG_PRINT("LCD_DATA output %d, DTR input %d",luat_gpio_get(LCD_DATA_PIN), luat_gpio_get(DTR_PIN));
+		luat_rtos_task_sleep(1000);
+		LUAT_DEBUG_PRINT("after high input, number of both interrupts %d", both_interrupt_cnt);
+
+		luat_gpio_set(LCD_DATA_PIN, 0);
+		LUAT_DEBUG_PRINT("LCD_DATA output %d, DTR input %d",luat_gpio_get(LCD_DATA_PIN), luat_gpio_get(DTR_PIN));
+		luat_rtos_task_sleep(1000);
+		LUAT_DEBUG_PRINT("after low input, number of both interrupts %d", both_interrupt_cnt);		
+	}	
+
+}
+
+void task_gpio_both_interrupt_init(void)
+{
+	luat_rtos_task_handle task_gpio_both_interrupt_handle;
+	luat_rtos_task_create(&task_gpio_both_interrupt_handle, 4 * 1204, 50, "gpio_both_interrupt_test", task_gpio_both_interrupt_run, NULL, 32);
+}
+int gpio_level_irq(void *data, void* args)
+{
+	int pin = (int)data;
+	LUAT_DEBUG_PRINT("pin:%d, level:%d,", pin, luat_gpio_get(pin));
+	luat_gpio_ctrl(DEMO_IRQ_PIN, LUAT_GPIO_CMD_SET_IRQ_MODE, LUAT_GPIO_NO_IRQ);
+}
+//GPIO电平中断测试
+void task_gpio_level_interrupt_run(void)
+{
+	luat_gpio_cfg_t gpio_cfg;
+
+	//配置HAL_GPIO_20为中断引脚
+	luat_gpio_set_default_cfg(&gpio_cfg);
+	gpio_cfg.pin = DEMO_IRQ_PIN;
+	gpio_cfg.mode = LUAT_GPIO_IRQ;
+
+	//DTR_PIN引脚支持双边沿或者高低电平类型的中断；
+	//所以此处可以配置为LUAT_GPIO_BOTH_IRQ、LUAT_GPIO_RISING_IRQ、LUAT_GPIO_FALLING_IRQ、LUAT_GPIO_HIGH_IRQ、LUAT_GPIO_LOW_IRQ、
+	gpio_cfg.irq_type = LUAT_GPIO_HIGH_IRQ;
+
+	gpio_cfg.pull = LUAT_GPIO_PULLUP;
+	gpio_cfg.irq_cb = gpio_level_irq;
+	luat_gpio_open(&gpio_cfg);
+
+	while(1)
+	{
+		if (!luat_gpio_get(DEMO_IRQ_PIN))
+		{
+			LUAT_DEBUG_PRINT("IO已经低电平，可以再次开启高电平中断");
+			luat_gpio_ctrl(DEMO_IRQ_PIN, LUAT_GPIO_CMD_SET_IRQ_MODE, LUAT_GPIO_HIGH_IRQ);
+		}
+		luat_rtos_task_sleep(1000);
+
+	}
+
+}
+
+void task_gpio_level_interrupt_init(void)
+{
+	luat_rtos_task_handle task_gpio_level_interrupt_handle;
+	luat_rtos_task_create(&task_gpio_level_interrupt_handle, 1024, 50, "gpio_level_interrupt_test", task_gpio_level_interrupt_run, NULL, 0);
+}
+
+
+
+INIT_TASK_EXPORT(task_gpio_output_init, "0");
+INIT_TASK_EXPORT(task_gpio_input_init, "1");
+INIT_TASK_EXPORT(task_gpio_single_interrupt_init, "2");
+INIT_TASK_EXPORT(task_gpio_both_interrupt_init, "3");
+INIT_TASK_EXPORT(task_gpio_level_interrupt_init, "4");
--- a/sdk/合宙/air780e/csdk/luatos-soc-2022/project/example_gpio/xmake.lua
+++ b/sdk/合宙/air780e/csdk/luatos-soc-2022/project/example_gpio/xmake.lua
@@ -0,0 +1,27 @@
+local TARGET_NAME = "example_gpio"
+local LIB_DIR = "$(buildir)/".. TARGET_NAME .. "/"
+local LIB_NAME = "lib" .. TARGET_NAME .. ".a "
+
+target(TARGET_NAME)
+    set_kind("static")
+    set_targetdir(LIB_DIR)
+    
+    --加入代码和头文件
+    add_includedirs("./inc",{public = true})
+    add_files("./src/*.c",{public = true})
+
+    --路径可以随便写,可以加任意路径的代码,下面代码等效上方代码
+    -- add_includedirs(SDK_TOP .. "project/" .. TARGET_NAME .. "/inc",{public = true})
+    -- add_files(SDK_TOP .. "project/" .. TARGET_NAME .. "/src/*.c",{public = true})
+
+    -- 按需链接mbedtls
+    -- add_defines("MBEDTLS_CONFIG_FILE=\"config_ec_ssl_comm.h\"")
+    -- add_files(SDK_TOP .. "PLAT/middleware/thirdparty/mbedtls/library/*.c")
+    -- 按需编译httpclient
+    -- add_files(SDK_TOP .. "PLAT/middleware/thirdparty/httpclient/*.c")
+
+    --可以继续增加add_includedirs和add_files
+    --自动链接
+    LIB_USER = LIB_USER .. SDK_TOP .. LIB_DIR .. LIB_NAME .. " "
+    --甚至可以加入自己的库
+target_end()