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更新硬件SDK

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kerwincui
2023-03-04 03:44:56 +08:00
parent dcdf6e1b7c
commit e39d3d2f03
1900 changed files with 663153 additions and 0 deletions
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354
sdk/合宙/air780e/csdk/luatos-soc-2022/project/example_socket/inc/RTE_Device.h Normal file
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#ifndef __RTE_DEVICE_H
#define __RTE_DEVICE_H
#include "ec618.h"
/* Peripheral IO Mode Select, Must Configure First !!!
Note, when receiver works in DMA_MODE, interrupt is also enabled to transfer tailing bytes.
*/
#define POLLING_MODE 0x1
#define DMA_MODE 0x2
#define IRQ_MODE 0x3
#define UNILOG_MODE 0x4
#define RTE_UART0_TX_IO_MODE UNILOG_MODE
#define RTE_UART0_RX_IO_MODE IRQ_MODE
#define USART0_RX_TRIG_LVL (30)
#define RTE_UART1_TX_IO_MODE DMA_MODE
#define RTE_UART1_RX_IO_MODE DMA_MODE
#define RTE_UART2_TX_IO_MODE DMA_MODE
#define RTE_UART2_RX_IO_MODE DMA_MODE
#define RTE_SPI0_IO_MODE POLLING_MODE
#define RTE_SPI1_IO_MODE POLLING_MODE
#define RTE_I2C0_IO_MODE POLLING_MODE
#define RTE_I2C1_IO_MODE POLLING_MODE
// I2C0 (Inter-integrated Circuit Interface) [Driver_I2C0]
// Configuration settings for Driver_I2C0 in component ::Drivers:I2C
#define RTE_I2C0 1
// { PAD_PIN13}, // 4 : gpio14 / 2 : I2C0 SCL
// { PAD_PIN14}, // 4 : gpio15 / 2 : I2C0 SDA
#define RTE_I2C0_SCL_BIT 13 // AUDIO use 13
#define RTE_I2C0_SCL_FUNC PAD_MUX_ALT2
#define RTE_I2C0_SDA_BIT 14 // AUDIO use 14
#define RTE_I2C0_SDA_FUNC PAD_MUX_ALT2
// DMA
// Tx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_I2C0_DMA_TX_EN 0
#define RTE_I2C0_DMA_TX_REQID DMA_REQUEST_I2C0_TX
// Rx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_I2C0_DMA_RX_EN 0
#define RTE_I2C0_DMA_RX_REQID DMA_REQUEST_I2C0_RX
// I2C1 (Inter-integrated Circuit Interface) [Driver_I2C1]
// Configuration settings for Driver_I2C1 in component ::Drivers:I2C
#define RTE_I2C1 1
// { PAD_PIN20}, // 0 : gpio5 / 2 : I2C1 SCL
// { PAD_PIN19}, // 0 : gpio4 / 2 : I2C1 SDA
#define RTE_I2C1_SCL_BIT 20
#define RTE_I2C1_SCL_FUNC PAD_MUX_ALT2
#define RTE_I2C1_SDA_BIT 19
#define RTE_I2C1_SDA_FUNC PAD_MUX_ALT2
// DMA
// Tx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_I2C1_DMA_TX_EN 1
#define RTE_I2C1_DMA_TX_REQID DMA_REQUEST_I2C1_TX
// Rx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_I2C1_DMA_RX_EN 1
#define RTE_I2C1_DMA_RX_REQID DMA_REQUEST_I2C1_RX
// UART0 (Universal asynchronous receiver transmitter) [Driver_USART0]
// Configuration settings for Driver_USART0 in component ::Drivers:USART
#define RTE_UART0_CTS_PIN_EN 0
#define RTE_UART0_RTS_PIN_EN 0
// { PAD_PIN27}, // 0 : gpio12 / 3 : UART0 RTSn
// { PAD_PIN28}, // 0 : gpio13 / 3 : UART0 CTSn
// { PAD_PIN29}, // 0 : gpio14 / 3 : UART0 RXD
// { PAD_PIN30}, // 0 : gpio15 / 3 : UART0 TXD
#define RTE_UART0_RTS_BIT 27
#define RTE_UART0_RTS_FUNC PAD_MUX_ALT3
#define RTE_UART0_CTS_BIT 28
#define RTE_UART0_CTS_FUNC PAD_MUX_ALT3
#define RTE_UART0_RX_BIT 29
#define RTE_UART0_RX_FUNC PAD_MUX_ALT3
#define RTE_UART0_TX_BIT 30
#define RTE_UART0_TX_FUNC PAD_MUX_ALT3
// DMA
// Tx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_UART0_DMA_TX_REQID DMA_REQUEST_USART0_TX
// Rx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_UART0_DMA_RX_REQID DMA_REQUEST_USART0_RX
// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
// Configuration settings for Driver_USART1 in component ::Drivers:USART
#define RTE_UART1_CTS_PIN_EN 0
#define RTE_UART1_RTS_PIN_EN 0
// { PAD_PIN31}, // 0 : gpio16 / 1 : UART1 RTS
// { PAD_PIN32}, // 0 : gpio17 / 1 : UART1 CTS
// { PAD_PIN33}, // 0 : gpio18 / 1 : UART1 RXD
// { PAD_PIN34}, // 0 : gpio19 / 1 : UART1 TXD
#define RTE_UART1_RTS_BIT 31
#define RTE_UART1_RTS_FUNC PAD_MUX_ALT1
#define RTE_UART1_CTS_BIT 32
#define RTE_UART1_CTS_FUNC PAD_MUX_ALT1
#define RTE_UART1_RX_BIT 33
#define RTE_UART1_RX_FUNC PAD_MUX_ALT1
#define RTE_UART1_TX_BIT 34
#define RTE_UART1_TX_FUNC PAD_MUX_ALT1
// DMA
// Tx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_UART1_DMA_TX_REQID DMA_REQUEST_USART1_TX
// Rx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_UART1_DMA_RX_REQID DMA_REQUEST_USART1_RX
// UART2 (Universal asynchronous receiver transmitter) [Driver_USART2]
// Configuration settings for Driver_USART2 in component ::Drivers:USART
#define RTE_UART2_CTS_PIN_EN 0
#define RTE_UART2_RTS_PIN_EN 0
// { PAD_PIN25}, // 0 : gpio10 / 3 : UART2 RXD
// { PAD_PIN26}, // 0 : gpio11 / 3 : UART2 TXD
#define RTE_UART2_RX_BIT 25
#define RTE_UART2_RX_FUNC PAD_MUX_ALT3
#define RTE_UART2_TX_BIT 26
#define RTE_UART2_TX_FUNC PAD_MUX_ALT3
// DMA
// Tx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_UART2_DMA_TX_REQID DMA_REQUEST_USART2_TX
// Rx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_UART2_DMA_RX_REQID DMA_REQUEST_USART2_RX
// SPI0 (Serial Peripheral Interface) [Driver_SPI0]
// Configuration settings for Driver_SPI0 in component ::Drivers:SPI
#define RTE_SPI0 1
// { PAD_PIN23}, // 0 : gpio8 / 1 : SPI0 SSn
// { PAD_PIN24}, // 0 : gpio9 / 1 : SPI0 MOSI
// { PAD_PIN25}, // 0 : gpio10 / 1 : SPI0 MISO
// { PAD_PIN26}, // 0 : gpio11 / 1 : SPI0 SCLK
#define RTE_SPI0_SSN_BIT 0xFF
#define RTE_SPI0_SSN_FUNC PAD_MUX_ALT1
#define RTE_SPI0_MOSI_BIT 24
#define RTE_SPI0_MOSI_FUNC PAD_MUX_ALT1
#define RTE_SPI0_MISO_BIT 25
#define RTE_SPI0_MISO_FUNC PAD_MUX_ALT1
#define RTE_SPI0_SCLK_BIT 26
#define RTE_SPI0_SCLK_FUNC PAD_MUX_ALT1
#define RTE_SPI0_SSN_GPIO_INSTANCE 0
#define RTE_SPI0_SSN_GPIO_INDEX 8
// DMA
// Tx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_SPI0_DMA_TX_REQID DMA_REQUEST_SPI0_TX
// Rx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_SPI0_DMA_RX_REQID DMA_REQUEST_SPI0_RX
// SPI1 (Serial Peripheral Interface) [Driver_SPI1]
// Configuration settings for Driver_SPI1 in component ::Drivers:SPI
#define RTE_SPI1 0
// { PAD_PIN27}, // 0 : gpio12 / 1 : SPI1 SSn
// { PAD_PIN28}, // 0 : gpio13 / 1 : SPI1 MOSI
// { PAD_PIN29}, // 0 : gpio14 / 1 : SPI1 MISO
// { PAD_PIN30}, // 0 : gpio15 / 1 : SPI1 SCLK
// { PAD_PIN31}, // 0 : gpio16 / 4 : SPI1 SSn1
#define RTE_SPI1_SSN_BIT 27
#define RTE_SPI1_SSN_FUNC PAD_MUX_ALT1
#define RTE_SPI1_MOSI_BIT 28
#define RTE_SPI1_MOSI_FUNC PAD_MUX_ALT1
#define RTE_SPI1_MISO_BIT 29
#define RTE_SPI1_MISO_FUNC PAD_MUX_ALT1
#define RTE_SPI1_SCLK_BIT 30
#define RTE_SPI1_SCLK_FUNC PAD_MUX_ALT1
#define RTE_SPI1_SSN_GPIO_INSTANCE 0
#define RTE_SPI1_SSN_GPIO_INDEX 12
#define RTE_SPI1_SSN1_BIT 31
#define RTE_SPI1_SSN1_FUNC PAD_MUX_ALT4
// DMA
// Tx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_SPI1_DMA_TX_REQID DMA_REQUEST_SPI1_TX
// Rx
// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
#define RTE_SPI1_DMA_RX_REQID DMA_REQUEST_SPI1_RX
// PWM0 Controller [Driver_PWM0]
// Configuration settings for Driver_PWM0 in component ::Drivers:PWM
#define RTE_PWM 1
#define EFUSE_INIT_MODE POLLING_MODE
#define L2CTLS_INIT_MODE POLLING_MODE
#define FLASH_BARE_RW_MODE 1
#define RTE_UART0 1
#define RTE_UART1 1
#define RTE_UART2 1
/* to enable external thermal */
#define EXTERNAL_NTC_EXIST 0
#if (RTE_UART1 == 1)
#define UART1_DTR_PAD_INDEX 26 // GPIO11
#define UART1_DTR_GPIO_INSTANCE 0
#define UART1_DTR_GPIO_PIN 11
#define UART1_RI_PAD_INDEX 44 // AONIO 4 = GPIO24
#define UART1_RI_GPIO_INSTANCE 1
#define UART1_RI_GPIO_PIN 8
#define UART1_RI_PWM_INSTANCE 1
#define UART1_RI_PWM_CLK_ID FCLK_TIMER1
#define UART1_RI_PWM_CLK_SEL FCLK_TIMER1_SEL_26M
#define UART1_DCD_PAD_INDEX 45 // AONIO 5 = GPIO25
#define UART1_DCD_GPIO_INSTANCE 1
#define UART1_DCD_GPIO_PIN 9
#endif
#if (RTE_UART2 == 1)
#define UART2_DTR_PAD_INDEX 25 // GPIO10
#define UART2_DTR_GPIO_INSTANCE 0
#define UART2_DTR_GPIO_PIN 10
#define UART2_RI_PAD_INDEX 43 // AONIO 3 = GPIO23
#define UART2_RI_GPIO_INSTANCE 1
#define UART2_RI_GPIO_PIN 7
#define UART2_RI_PWM_INSTANCE 0
#define UART2_RI_PWM_CLK_ID FCLK_TIMER0
#define UART2_RI_PWM_CLK_SEL FCLK_TIMER0_SEL_26M
#define UART2_DCD_PAD_INDEX 47 // AONIO 7 = GPIO27
#define UART2_DCD_GPIO_INSTANCE 1
#define UART2_DCD_GPIO_PIN 11
#endif
#define NETLIGHT_PAD_INDEX 46 // AONIO 6 = GPIO26
#define NETLIGHT_PAD_ALT_FUNC PAD_MUX_ALT5
#define NETLIGHT_PWM_INSTANCE 3
//USIM1 OPTION1
#define USIM1_URST_OP1_PAD_INDEX 19 // GPIO4
#define USIM1_URST_OP1_GPIO_INSTANCE 0
#define USIM1_URST_OP1_GPIO_PIN 4
#define USIM1_UCLK_OP1_PAD_INDEX 20 // GPIO5
#define USIM1_UCLK_OP1_GPIO_INSTANCE 0
#define USIM1_UCLK_OP1_GPIO_PIN 5
#define USIM1_UIO_OP1_PAD_INDEX 21 // GPIO6
#define USIM1_UIO_OP1_GPIO_INSTANCE 0
#define USIM1_UIO_OP1_GPIO_PIN 6
//USIM1 OPTION2
#define USIM1_UIO_OP2_PAD_INDEX 27 // GPIO12
#define USIM1_UIO_OP2_GPIO_INSTANCE 0
#define USIM1_UIO_OP2_GPIO_PIN 12
#define USIM1_URST_OP2_PAD_INDEX 28 // GPIO13
#define USIM1_URST_OP2_GPIO_INSTANCE 0
#define USIM1_URST_OP2_GPIO_PIN 13
#define USIM1_UCLK_OP2_PAD_INDEX 29 // GPIO14
#define USIM1_UCLK_OP2_GPIO_INSTANCE 0
#define USIM1_UCLK_OP2_GPIO_PIN 14
//USIM1 clock latched by AONIO, for example, use AONIO-6 test on EVB
#define AONIO_6_PAD_INDEX 46 // AONIO 6 = GPIO26
#define AONIO_6_GPIO_INSTANCE 1
#define AONIO_6_GPIO_PIN 10
#define RTE_CSPI0 0
#define RTE_CSPI0_MCLK_PAD_ADDR 39
#define RTE_CSPI0_MCLK_FUNC PAD_MUX_ALT1
#define RTE_CSPI0_PCLK_PAD_ADDR 35
#define RTE_CSPI0_PCLK_FUNC PAD_MUX_ALT1
#define RTE_CSPI0_CS_PAD_ADDR 36
#define RTE_CSPI0_CS_FUNC PAD_MUX_ALT1
#define RTE_CSPI0_SDO0_PAD_ADDR 37
#define RTE_CSPI0_SDO0_FUNC PAD_MUX_ALT1
#define RTE_CSPI0_SDO1_PAD_ADDR 38
#define RTE_CSPI0_SDO1_FUNC PAD_MUX_ALT1
// DMA CSPI0 Request ID
#define RTE_CSPI0_DMA_RX_REQID DMA_REQUEST_I2S0_RX
// CSPI1 Configuration
#define RTE_CSPI1 1
#define RTE_CSPI1_MCLK_PAD_ADDR 18
#define RTE_CSPI1_MCLK_FUNC PAD_MUX_ALT1
#define RTE_CSPI1_PCLK_PAD_ADDR 19
#define RTE_CSPI1_PCLK_FUNC PAD_MUX_ALT1
#define RTE_CSPI1_CS_PAD_ADDR 20
#define RTE_CSPI1_CS_FUNC PAD_MUX_ALT1
#define RTE_CSPI1_SDO0_PAD_ADDR 21
#define RTE_CSPI1_SDO0_FUNC PAD_MUX_ALT1
#define RTE_CSPI1_SDO1_PAD_ADDR 22
#define RTE_CSPI1_SDO1_FUNC PAD_MUX_ALT1
// DMA CSPI1 Request ID
#define RTE_CSPI1_DMA_RX_REQID DMA_REQUEST_I2S1_RX
#endif /* __RTE_DEVICE_H */

352
sdk/合宙/air780e/csdk/luatos-soc-2022/project/example_socket/src/example_socket.c Normal file
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#include "common_api.h"
#include "sockets.h"
#include "dns.h"
#include "lwip/ip4_addr.h"
#include "netdb.h"
#include "luat_debug.h"
#include "luat_rtos.h"
#include "luat_mobile.h"
#define DEMO_SERVER_TCP_IP "112.125.89.8"
#define DEMO_SERVER_TCP_PORT 34019
#define DEMO_SERVER_UDP_IP "112.125.89.8"
#define DEMO_SERVER_UDP_PORT 35690
typedef struct
{
uint8_t is_link_up;
}demo_ctrl_t;
static demo_ctrl_t g_s_demo;
static void demo_tcp_task(void *arg)
{
ip_addr_t remote_ip;
char *rxbuf;
struct sockaddr_in name;
socklen_t sockaddr_t_size = sizeof(name);
fd_set write_set, read_set, error_set;
int ret;
struct timeval to;
uint8_t is_connect, is_read;
int socket_id = -1;
struct hostent dns_result;
struct hostent *p_result;
int h_errnop, read_len;
while(1)
{
while(!g_s_demo.is_link_up)
{
luat_rtos_task_sleep(1000);
}
char buf[128] = {0};
ret = lwip_gethostbyname_r(DEMO_SERVER_TCP_IP, &dns_result, buf, 128, &p_result, &h_errnop);
if (!ret)
{
remote_ip = *((ip_addr_t *)dns_result.h_addr_list[0]);
}
else
{
luat_rtos_task_sleep(1000);
LUAT_DEBUG_PRINT("dns fail");
continue;
}
socket_id = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP);
fcntl(socket_id, F_SETFL, O_NONBLOCK);
memset(&name, 0, sizeof(name));
name.sin_family = AF_INET;
name.sin_addr.s_addr = IPADDR_ANY;
name.sin_port = 0;
//LUAT_DEBUG_PRINT("%x", name.sin_addr.s_addr);
bind(socket_id, (const struct sockaddr *)&name, sockaddr_t_size);
name.sin_family = AF_INET;
name.sin_addr.s_addr = remote_ip.u_addr.ip4.addr;
name.sin_port = htons(DEMO_SERVER_TCP_PORT);
ret = connect(socket_id, (const struct sockaddr *)&name, sockaddr_t_size);
to.tv_sec = 30;
to.tv_usec = 0;
FD_ZERO(&write_set);
FD_ZERO(&error_set);
FD_SET(socket_id,&write_set);
FD_SET(socket_id,&error_set);
ret = select(socket_id+1, NULL, &write_set, &error_set, &to);
if(ret < 0)
{
is_connect = 0;
}
else if(ret == 0)
{
is_connect = 0;
}
else
{
if(FD_ISSET(socket_id, &error_set))
{
is_connect = 0;
}
else if(FD_ISSET(socket_id, &write_set))
{
is_connect = 1;
}
}
if (is_connect)
{
LUAT_DEBUG_PRINT("socket connect ok");
rxbuf = malloc(1024);
send(socket_id, "helloworld", 10, 0);
is_read = 0;
while(is_connect)
{
FD_ZERO(&read_set);
FD_ZERO(&error_set);
FD_SET(socket_id,&read_set);
FD_SET(socket_id,&error_set);
to.tv_sec = 60;
to.tv_usec = 0;
ret = select(socket_id+1, &read_set, NULL, &error_set, &to);
if(ret < 0)
{
is_connect = 0;
}
else if(ret == 0)
{
is_read = 0;
}
else
{
if(FD_ISSET(socket_id, &error_set))
{
is_connect = 0;
}
else if(FD_ISSET(socket_id, &read_set))
{
is_read = 1;
}
}
if (is_connect)
{
if (is_read)
{
do
{
read_len = recv(socket_id, rxbuf, 1024, 0);
if (read_len > 0)
{
send(socket_id, rxbuf, read_len, 0);
}
}while(read_len > 0);
}
else
{
send(socket_id, "heart", 5, 0);
}
}
}
free(rxbuf);
}
LUAT_DEBUG_PRINT("socket quit");
close(socket_id);
socket_id = -1;
luat_rtos_task_sleep(5000);
}
}
static void demo_udp_task(void *arg)
{
ip_addr_t remote_ip;
char *rxbuf;
struct sockaddr_in name;
struct sockaddr_in from;
socklen_t from_len;
socklen_t sockaddr_t_size = sizeof(name);
fd_set write_set, read_set, error_set;
int ret;
struct timeval to;
uint8_t is_connect, is_read;
int socket_id = -1;
struct hostent dns_result;
struct hostent *p_result;
int h_errnop, read_len;
while(1)
{
while(!g_s_demo.is_link_up)
{
luat_rtos_task_sleep(1000);
}
char buf[128] = {0};
ret = lwip_gethostbyname_r(DEMO_SERVER_UDP_IP, &dns_result, buf, 128, &p_result, &h_errnop);
if (!ret)
{
remote_ip = *((ip_addr_t *)dns_result.h_addr_list[0]);
}
else
{
luat_rtos_task_sleep(1000);
LUAT_DEBUG_PRINT("dns fail");
continue;
}
socket_id = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);
fcntl(socket_id, F_SETFL, O_NONBLOCK);
memset(&name, 0, sizeof(name));
name.sin_family = AF_INET;
name.sin_addr.s_addr = IPADDR_ANY;
name.sin_port = 0;
//LUAT_DEBUG_PRINT("%x", name.sin_addr.s_addr);
bind(socket_id, (const struct sockaddr *)&name, sockaddr_t_size);
name.sin_family = AF_INET;
name.sin_addr.s_addr = remote_ip.u_addr.ip4.addr;
name.sin_port = htons(DEMO_SERVER_UDP_PORT);
is_connect = 1;
if (is_connect)
{
LUAT_DEBUG_PRINT("socket connect ok");
rxbuf = malloc(1024);
sendto(socket_id, "helloworld", 10, 0, (const struct sockaddr *)&name, sockaddr_t_size);
is_read = 0;
while(is_connect)
{
FD_ZERO(&read_set);
FD_ZERO(&error_set);
FD_SET(socket_id,&read_set);
FD_SET(socket_id,&error_set);
to.tv_sec = 60;
to.tv_usec = 0;
ret = select(socket_id+1, &read_set, NULL, &error_set, &to);
if(ret < 0)
{
is_connect = 0;
}
else if(ret == 0)
{
is_read = 0;
}
else
{
if(FD_ISSET(socket_id, &error_set))
{
is_connect = 0;
}
else if(FD_ISSET(socket_id, &read_set))
{
is_read = 1;
}
}
if (is_connect)
{
if (is_read)
{
do
{
read_len = recvfrom(socket_id, rxbuf, 1024, 0, &from, &from_len);
if (read_len > 0)
{
sendto(socket_id, rxbuf, read_len, 0, (const struct sockaddr *)&name, sockaddr_t_size);
}
}while(read_len > 0);
}
else
{
sendto(socket_id, "heart", 5, 0, (const struct sockaddr *)&name, sockaddr_t_size);
}
}
}
free(rxbuf);
}
LUAT_DEBUG_PRINT("socket quit");
close(socket_id);
socket_id = -1;
luat_rtos_task_sleep(5000);
}
}
static void demo_tcp_init(void)
{
luat_rtos_task_handle tcp_task_handle;
luat_rtos_task_create(&tcp_task_handle, 2048, 20, "tcp", demo_tcp_task, NULL, NULL);
}
static void demo_udp_init(void)
{
luat_rtos_task_handle tcp_task_handle;
luat_rtos_task_create(&tcp_task_handle, 2048, 20, "udp", demo_udp_task, NULL, NULL);
}
static void mobile_event_cb(LUAT_MOBILE_EVENT_E event, uint8_t index, uint8_t status)
{
switch(event)
{
case LUAT_MOBILE_EVENT_CFUN:
LUAT_DEBUG_PRINT("CFUN消息，status %d", status);
break;
case LUAT_MOBILE_EVENT_SIM:
LUAT_DEBUG_PRINT("SIM卡消息");
switch(status)
{
case LUAT_MOBILE_SIM_READY:
LUAT_DEBUG_PRINT("SIM卡正常工作");
break;
case LUAT_MOBILE_NO_SIM:
LUAT_DEBUG_PRINT("SIM卡不存在");
break;
case LUAT_MOBILE_SIM_NEED_PIN:
LUAT_DEBUG_PRINT("SIM卡需要输入PIN码");
break;
}
break;
case LUAT_MOBILE_EVENT_REGISTER_STATUS:
LUAT_DEBUG_PRINT("移动网络服务状态变更，当前为%d", status);
break;
case LUAT_MOBILE_EVENT_CELL_INFO:
switch(status)
{
case LUAT_MOBILE_CELL_INFO_UPDATE:
break;
case LUAT_MOBILE_SIGNAL_UPDATE:
break;
}
break;
case LUAT_MOBILE_EVENT_PDP:
LUAT_DEBUG_PRINT("CID %d PDP激活状态变更为 %d", index, status);
break;
case LUAT_MOBILE_EVENT_NETIF:
LUAT_DEBUG_PRINT("internet工作状态变更为 %d", status);
switch (status)
{
case LUAT_MOBILE_NETIF_LINK_ON:
LUAT_DEBUG_PRINT("可以上网");
g_s_demo.is_link_up = 1;
break;
default:
LUAT_DEBUG_PRINT("不能上网");
g_s_demo.is_link_up = 0;
break;
}
break;
case LUAT_MOBILE_EVENT_TIME_SYNC:
LUAT_DEBUG_PRINT("通过移动网络同步了UTC时间");
break;
case LUAT_MOBILE_EVENT_CSCON:
LUAT_DEBUG_PRINT("RRC状态 %d", status);
break;
default:
break;
}
}
void task_init(void)
{
luat_mobile_event_register_handler(mobile_event_cb);
}
INIT_HW_EXPORT(task_init, "0");
INIT_TASK_EXPORT(demo_tcp_init, "1");
INIT_TASK_EXPORT(demo_udp_init, "2");

27
sdk/合宙/air780e/csdk/luatos-soc-2022/project/example_socket/xmake.lua Normal file
View File

@@ -0,0 +1,27 @@
local TARGET_NAME = "example_socket"
local LIB_DIR = "$(buildir)/".. TARGET_NAME .. "/"
local LIB_NAME = "lib" .. TARGET_NAME .. ".a "
target(TARGET_NAME)
set_kind("static")
set_targetdir(LIB_DIR)
--加入代码和头文件
add_includedirs("./inc",{public = true})
add_files("./src/*.c",{public = true})
--路径可以随便写,可以加任意路径的代码,下面代码等效上方代码
-- add_includedirs(SDK_TOP .. "project/" .. TARGET_NAME .. "/inc",{public = true})
-- add_files(SDK_TOP .. "project/" .. TARGET_NAME .. "/src/*.c",{public = true})
-- 按需链接mbedtls
-- add_defines("MBEDTLS_CONFIG_FILE=\"config_ec_ssl_comm.h\"")
-- add_files(SDK_TOP .. "PLAT/middleware/thirdparty/mbedtls/library/*.c")
-- 按需编译httpclient
-- add_files(SDK_TOP .. "PLAT/middleware/thirdparty/httpclient/*.c")
--可以继续增加add_includedirs和add_files
--自动链接
LIB_USER = LIB_USER .. SDK_TOP .. LIB_DIR .. LIB_NAME
--甚至可以加入自己的库
target_end()