mirror of
https://gitee.com/beecue/fastbee.git
synced 2025-12-20 18:05:54 +08:00
更新硬件SDK
This commit is contained in:
kerwincui
@@ -0,0 +1,350 @@
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#ifndef __RTE_DEVICE_H
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#define __RTE_DEVICE_H
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#include "ec618.h"
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/* Peripheral IO Mode Select, Must Configure First !!!
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Note, when receiver works in DMA_MODE, interrupt is also enabled to transfer tailing bytes.
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*/
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#define POLLING_MODE 0x1
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#define DMA_MODE 0x2
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#define IRQ_MODE 0x3
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#define UNILOG_MODE 0x4
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#define RTE_UART0_TX_IO_MODE UNILOG_MODE
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#define RTE_UART0_RX_IO_MODE IRQ_MODE
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#define USART0_RX_TRIG_LVL (30)
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#define RTE_UART1_TX_IO_MODE DMA_MODE
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#define RTE_UART1_RX_IO_MODE DMA_MODE
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#define RTE_UART2_TX_IO_MODE POLLING_MODE
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#define RTE_UART2_RX_IO_MODE DMA_MODE
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#define RTE_SPI0_IO_MODE POLLING_MODE
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#define RTE_SPI1_IO_MODE POLLING_MODE
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#define RTE_I2C0_IO_MODE POLLING_MODE
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#define RTE_I2C1_IO_MODE POLLING_MODE
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// I2C0 (Inter-integrated Circuit Interface) [Driver_I2C0]
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// Configuration settings for Driver_I2C0 in component ::Drivers:I2C
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#define RTE_I2C0 1
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// { PAD_PIN28}, // 0 : gpio13 / 2 : I2C0 SCL
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// { PAD_PIN27}, // 0 : gpio12 / 2 : I2C0 SDA
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#define RTE_I2C0_SCL_BIT 28 // AUDIO use 28
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#define RTE_I2C0_SCL_FUNC PAD_MUX_ALT2
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#define RTE_I2C0_SDA_BIT 27 // AUDIO use 27
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#define RTE_I2C0_SDA_FUNC PAD_MUX_ALT2
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// DMA
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// Tx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_I2C0_DMA_TX_EN 0
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#define RTE_I2C0_DMA_TX_REQID DMA_REQUEST_I2C0_TX
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// Rx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_I2C0_DMA_RX_EN 0
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#define RTE_I2C0_DMA_RX_REQID DMA_REQUEST_I2C0_RX
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// I2C1 (Inter-integrated Circuit Interface) [Driver_I2C1]
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// Configuration settings for Driver_I2C1 in component ::Drivers:I2C
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#define RTE_I2C1 1
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// { PAD_PIN20}, // 0 : gpio5 / 2 : I2C1 SCL
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// { PAD_PIN19}, // 0 : gpio4 / 2 : I2C1 SDA
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#define RTE_I2C1_SCL_BIT 20
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#define RTE_I2C1_SCL_FUNC PAD_MUX_ALT2
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#define RTE_I2C1_SDA_BIT 19
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#define RTE_I2C1_SDA_FUNC PAD_MUX_ALT2
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// DMA
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// Tx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_I2C1_DMA_TX_EN 1
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#define RTE_I2C1_DMA_TX_REQID DMA_REQUEST_I2C1_TX
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// Rx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_I2C1_DMA_RX_EN 1
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#define RTE_I2C1_DMA_RX_REQID DMA_REQUEST_I2C1_RX
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// UART0 (Universal asynchronous receiver transmitter) [Driver_USART0]
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// Configuration settings for Driver_USART0 in component ::Drivers:USART
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#define RTE_UART0_CTS_PIN_EN 0
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#define RTE_UART0_RTS_PIN_EN 0
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// { PAD_PIN27}, // 0 : gpio12 / 3 : UART0 RTSn
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// { PAD_PIN28}, // 0 : gpio13 / 3 : UART0 CTSn
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// { PAD_PIN29}, // 0 : gpio14 / 3 : UART0 RXD
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// { PAD_PIN30}, // 0 : gpio15 / 3 : UART0 TXD
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#define RTE_UART0_RTS_BIT 27
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#define RTE_UART0_RTS_FUNC PAD_MUX_ALT3
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#define RTE_UART0_CTS_BIT 28
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#define RTE_UART0_CTS_FUNC PAD_MUX_ALT3
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#define RTE_UART0_RX_BIT 29
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#define RTE_UART0_RX_FUNC PAD_MUX_ALT3
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#define RTE_UART0_TX_BIT 30
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#define RTE_UART0_TX_FUNC PAD_MUX_ALT3
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// DMA
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// Tx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_UART0_DMA_TX_REQID DMA_REQUEST_USART0_TX
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// Rx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_UART0_DMA_RX_REQID DMA_REQUEST_USART0_RX
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// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
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// Configuration settings for Driver_USART1 in component ::Drivers:USART
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#define RTE_UART1_CTS_PIN_EN 1
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#define RTE_UART1_RTS_PIN_EN 1
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// { PAD_PIN31}, // 0 : gpio16 / 1 : UART1 RTS
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// { PAD_PIN32}, // 0 : gpio17 / 1 : UART1 CTS
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// { PAD_PIN33}, // 0 : gpio18 / 1 : UART1 RXD
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// { PAD_PIN34}, // 0 : gpio19 / 1 : UART1 TXD
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#define RTE_UART1_RTS_BIT 31
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#define RTE_UART1_RTS_FUNC PAD_MUX_ALT1
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#define RTE_UART1_CTS_BIT 32
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#define RTE_UART1_CTS_FUNC PAD_MUX_ALT1
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#define RTE_UART1_RX_BIT 33
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#define RTE_UART1_RX_FUNC PAD_MUX_ALT1
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#define RTE_UART1_TX_BIT 34
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#define RTE_UART1_TX_FUNC PAD_MUX_ALT1
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// DMA
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// Tx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_UART1_DMA_TX_REQID DMA_REQUEST_USART1_TX
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// Rx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_UART1_DMA_RX_REQID DMA_REQUEST_USART1_RX
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// UART2 (Universal asynchronous receiver transmitter) [Driver_USART2]
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// Configuration settings for Driver_USART2 in component ::Drivers:USART
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#define RTE_UART2_CTS_PIN_EN 0
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#define RTE_UART2_RTS_PIN_EN 0
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// { PAD_PIN25}, // 0 : gpio10 / 3 : UART2 RXD
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// { PAD_PIN26}, // 0 : gpio11 / 3 : UART2 TXD
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#define RTE_UART2_RX_BIT 25
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#define RTE_UART2_RX_FUNC PAD_MUX_ALT3
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#define RTE_UART2_TX_BIT 26
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#define RTE_UART2_TX_FUNC PAD_MUX_ALT3
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// DMA
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// Tx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_UART2_DMA_TX_REQID DMA_REQUEST_USART2_TX
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// Rx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_UART2_DMA_RX_REQID DMA_REQUEST_USART2_RX
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// SPI0 (Serial Peripheral Interface) [Driver_SPI0]
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// Configuration settings for Driver_SPI0 in component ::Drivers:SPI
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#define RTE_SPI0 1
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// { PAD_PIN21}, // 0 : gpio16 / 1 : UART1 RTS / 2 : SPI0 SSn
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// { PAD_PIN22}, // 0 : gpio11 / 1 : UART1 CTS / 2 : SPI0 MOSI
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// { PAD_PIN23}, // 0 : gpio14 / 1 : UART1 RXD / 2 : SPI0 MISO
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// { PAD_PIN24}, // 0 : gpio15 / 1 : UART1 TXD / 2 : SPI0 SCLK
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#define RTE_SPI0_SSN_BIT 21
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#define RTE_SPI0_SSN_FUNC PAD_MUX_ALT2
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#define RTE_SPI0_MOSI_BIT 22
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#define RTE_SPI0_MOSI_FUNC PAD_MUX_ALT2
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#define RTE_SPI0_MISO_BIT 23
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#define RTE_SPI0_MISO_FUNC PAD_MUX_ALT2
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#define RTE_SPI0_SCLK_BIT 24
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#define RTE_SPI0_SCLK_FUNC PAD_MUX_ALT2
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#define RTE_SPI0_SSN_GPIO_INSTANCE 1
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#define RTE_SPI0_SSN_GPIO_INDEX 0
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// DMA
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// Tx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_SPI0_DMA_TX_REQID DMA_REQUEST_SPI0_TX
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// Rx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_SPI0_DMA_RX_REQID DMA_REQUEST_SPI0_RX
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// SPI1 (Serial Peripheral Interface) [Driver_SPI1]
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// Configuration settings for Driver_SPI1 in component ::Drivers:SPI
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#define RTE_SPI1 1
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// { PAD_PIN13}, // 0 : gpio2 / 1 : UART0 RTSn / 3 : SPI1 SSn
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// { PAD_PIN14}, // 0 : gpio3 / 1 : UART0 CTSn / 3 : SPI1 MOSI
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// { PAD_PIN15}, // 0 : gpio4 / 1 : UART0 RXD / 3 : SPI1 MISO
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// { PAD_PIN16}, // 0 : gpio5 / 1 : UART0 TXD / 3 : SPI1 SCLK
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#define RTE_SPI1_SSN_BIT 13
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#define RTE_SPI1_SSN_FUNC PAD_MUX_ALT3
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#define RTE_SPI1_MOSI_BIT 14
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#define RTE_SPI1_MOSI_FUNC PAD_MUX_ALT3
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#define RTE_SPI1_MISO_BIT 15
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#define RTE_SPI1_MISO_FUNC PAD_MUX_ALT3
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#define RTE_SPI1_SCLK_BIT 16
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#define RTE_SPI1_SCLK_FUNC PAD_MUX_ALT3
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#define RTE_SPI1_SSN_GPIO_INSTANCE 0
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#define RTE_SPI1_SSN_GPIO_INDEX 2
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// DMA
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// Tx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_SPI1_DMA_TX_REQID DMA_REQUEST_SPI1_TX
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// Rx
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// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
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#define RTE_SPI1_DMA_RX_REQID DMA_REQUEST_SPI1_RX
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// PWM0 Controller [Driver_PWM0]
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// Configuration settings for Driver_PWM0 in component ::Drivers:PWM
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#define RTE_PWM 1
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#define EFUSE_INIT_MODE POLLING_MODE
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#define L2CTLS_INIT_MODE POLLING_MODE
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#define FLASH_BARE_RW_MODE 1
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#define RTE_UART0 1
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#define RTE_UART1 1
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#define RTE_UART2 1
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/* to enable external thermal */
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#define EXTERNAL_NTC_EXIST 0
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#if (RTE_UART1 == 1)
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#define UART1_DTR_PAD_INDEX 26 // GPIO11
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#define UART1_DTR_GPIO_INSTANCE 0
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#define UART1_DTR_GPIO_PIN 11
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#define UART1_RI_PAD_INDEX 44 // AONIO 4 = GPIO24
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#define UART1_RI_GPIO_INSTANCE 1
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#define UART1_RI_GPIO_PIN 8
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#define UART1_RI_PWM_INSTANCE 1
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#define UART1_RI_PWM_CLK_ID FCLK_TIMER1
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#define UART1_RI_PWM_CLK_SEL FCLK_TIMER1_SEL_26M
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#define UART1_DCD_PAD_INDEX 45 // AONIO 5 = GPIO25
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#define UART1_DCD_GPIO_INSTANCE 1
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#define UART1_DCD_GPIO_PIN 9
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#endif
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#if (RTE_UART2 == 1)
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#define UART2_DTR_PAD_INDEX 25 // GPIO10
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#define UART2_DTR_GPIO_INSTANCE 0
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#define UART2_DTR_GPIO_PIN 10
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#define UART2_RI_PAD_INDEX 43 // AONIO 3 = GPIO23
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#define UART2_RI_GPIO_INSTANCE 1
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#define UART2_RI_GPIO_PIN 7
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#define UART2_RI_PWM_INSTANCE 0
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#define UART2_RI_PWM_CLK_ID FCLK_TIMER0
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#define UART2_RI_PWM_CLK_SEL FCLK_TIMER0_SEL_26M
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#define UART2_DCD_PAD_INDEX 47 // AONIO 7 = GPIO27
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#define UART2_DCD_GPIO_INSTANCE 1
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#define UART2_DCD_GPIO_PIN 11
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#endif
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#define NETLIGHT_PAD_INDEX 46 // AONIO 6 = GPIO26
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#define NETLIGHT_PAD_ALT_FUNC PAD_MUX_ALT5
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#define NETLIGHT_PWM_INSTANCE 3
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//USIM1 OPTION1
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#define USIM1_URST_OP1_PAD_INDEX 19 // GPIO4
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#define USIM1_URST_OP1_GPIO_INSTANCE 0
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#define USIM1_URST_OP1_GPIO_PIN 4
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#define USIM1_UCLK_OP1_PAD_INDEX 20 // GPIO5
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#define USIM1_UCLK_OP1_GPIO_INSTANCE 0
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#define USIM1_UCLK_OP1_GPIO_PIN 5
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#define USIM1_UIO_OP1_PAD_INDEX 21 // GPIO6
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#define USIM1_UIO_OP1_GPIO_INSTANCE 0
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#define USIM1_UIO_OP1_GPIO_PIN 6
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//USIM1 OPTION2
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#define USIM1_UIO_OP2_PAD_INDEX 27 // GPIO12
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#define USIM1_UIO_OP2_GPIO_INSTANCE 0
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#define USIM1_UIO_OP2_GPIO_PIN 12
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#define USIM1_URST_OP2_PAD_INDEX 28 // GPIO13
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#define USIM1_URST_OP2_GPIO_INSTANCE 0
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#define USIM1_URST_OP2_GPIO_PIN 13
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#define USIM1_UCLK_OP2_PAD_INDEX 29 // GPIO14
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#define USIM1_UCLK_OP2_GPIO_INSTANCE 0
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#define USIM1_UCLK_OP2_GPIO_PIN 14
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//USIM1 clock latched by AONIO, for example, use AONIO-6 test on EVB
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#define AONIO_6_PAD_INDEX 46 // AONIO 6 = GPIO26
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#define AONIO_6_GPIO_INSTANCE 1
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#define AONIO_6_GPIO_PIN 10
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#define RTE_CSPI0 0
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#define RTE_CSPI0_MCLK_PAD_ADDR 39
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#define RTE_CSPI0_MCLK_FUNC PAD_MUX_ALT1
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#define RTE_CSPI0_PCLK_PAD_ADDR 35
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#define RTE_CSPI0_PCLK_FUNC PAD_MUX_ALT1
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#define RTE_CSPI0_CS_PAD_ADDR 36
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#define RTE_CSPI0_CS_FUNC PAD_MUX_ALT1
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#define RTE_CSPI0_SDO0_PAD_ADDR 37
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#define RTE_CSPI0_SDO0_FUNC PAD_MUX_ALT1
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#define RTE_CSPI0_SDO1_PAD_ADDR 38
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#define RTE_CSPI0_SDO1_FUNC PAD_MUX_ALT1
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// DMA CSPI0 Request ID
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#define RTE_CSPI0_DMA_RX_REQID DMA_REQUEST_I2S0_RX
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// CSPI1 Configuration
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#define RTE_CSPI1 1
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#define RTE_CSPI1_MCLK_PAD_ADDR 18
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#define RTE_CSPI1_MCLK_FUNC PAD_MUX_ALT1
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#define RTE_CSPI1_PCLK_PAD_ADDR 19
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#define RTE_CSPI1_PCLK_FUNC PAD_MUX_ALT1
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#define RTE_CSPI1_CS_PAD_ADDR 20
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#define RTE_CSPI1_CS_FUNC PAD_MUX_ALT1
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#define RTE_CSPI1_SDO0_PAD_ADDR 21
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#define RTE_CSPI1_SDO0_FUNC PAD_MUX_ALT1
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#define RTE_CSPI1_SDO1_PAD_ADDR 22
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#define RTE_CSPI1_SDO1_FUNC PAD_MUX_ALT1
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// DMA CSPI1 Request ID
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#define RTE_CSPI1_DMA_RX_REQID DMA_REQUEST_I2S1_RX
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#endif /* __RTE_DEVICE_H */
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@@ -0,0 +1,161 @@
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/*
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||||
* Copyright (c) 2022 OpenLuat & AirM2M
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
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||||
|
||||
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||||
#include "common_api.h"
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||||
#include "FreeRTOS.h"
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||||
#include "task.h"
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||||
|
||||
#include "ps_event_callback.h"
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||||
#include "ps_lib_api.h"
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||||
#include "sockets.h"
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||||
#include "networkmgr.h"
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||||
#include "netdb.h"
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||||
#include "slpman.h"
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||||
#include "time.h"
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||||
#include "sntp.h"
|
||||
#include "plat_config.h"
|
||||
#include "semphr.h"
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||||
typedef struct
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||||
{
|
||||
ip_addr_t remote_ip;
|
||||
ip_addr_t local_ip;
|
||||
void *wait_link_sem;
|
||||
void *wait_dns_sem;
|
||||
void *heart_timer;
|
||||
void *pa_delay_timer;
|
||||
int socket_id;
|
||||
uint8_t is_link_up;
|
||||
uint8_t ipv4_cid;
|
||||
uint8_t ipv6_cid;
|
||||
}demo_ctrl_t;
|
||||
|
||||
static demo_ctrl_t g_s_demo;
|
||||
|
||||
static INT32 ps_callback(PsEventID eventID, void *param, UINT32 paramLen)
|
||||
{
|
||||
CmiSimImsiStr *imsi = NULL;
|
||||
CmiPsCeregInd *creg = NULL;
|
||||
NmAtiNetInfoInd *net_info = NULL;
|
||||
|
||||
switch(eventID)
|
||||
{
|
||||
case PS_URC_ID_SIM_READY:
|
||||
{
|
||||
imsi = (CmiSimImsiStr *)param;
|
||||
DBG("SIM ready(imsi=%s len=%d)", imsi->contents, imsi->length);
|
||||
break;
|
||||
}
|
||||
case PS_URC_ID_PS_BEARER_ACTED:
|
||||
{
|
||||
DBG("Default bearer activated");
|
||||
break;
|
||||
}
|
||||
case PS_URC_ID_PS_BEARER_DEACTED:
|
||||
{
|
||||
DBG("Default bearer Deactivated");
|
||||
break;
|
||||
}
|
||||
case PS_URC_ID_PS_CEREG_CHANGED:
|
||||
{
|
||||
creg = (CmiPsCeregInd *)param;
|
||||
DBG("CREG message act:%d celId:%d locPresent:%d state:%d", creg->act, creg->celId, creg->locPresent, creg->state);
|
||||
break;
|
||||
}
|
||||
case PS_URC_ID_PS_NETINFO:
|
||||
{
|
||||
net_info = (NmAtiNetInfoInd *)param;
|
||||
DBG("%d,%d,%d,%d", net_info->indCause, net_info->netifInfo.netStatus, net_info->netifInfo.ipv4Cid, net_info->netifInfo.ipv6Cid);
|
||||
switch(net_info->indCause)
|
||||
{
|
||||
case NM_STATUS_CHANGE_LINK_UP:
|
||||
case NM_STATUS_CHANGE_LINK_UP_IPV4:
|
||||
case NM_STATUS_CHANGE_LINK_UP_IPV6:
|
||||
case NM_STATUS_CHANGE_RA_SUCCESS:
|
||||
DBG("network ready");
|
||||
if (!g_s_demo.is_link_up)
|
||||
{
|
||||
g_s_demo.is_link_up = 1;
|
||||
xSemaphoreGive(g_s_demo.wait_link_sem);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
g_s_demo.is_link_up = 0;
|
||||
DBG("network not ready");
|
||||
break;
|
||||
}
|
||||
|
||||
if (NM_NETIF_ACTIVATED == net_info->netifInfo.netStatus)
|
||||
{
|
||||
g_s_demo.ipv4_cid = net_info->netifInfo.ipv4Cid;
|
||||
g_s_demo.ipv6_cid = net_info->netifInfo.ipv6Cid;
|
||||
g_s_demo.local_ip.type = IPADDR_TYPE_V4;
|
||||
g_s_demo.local_ip.u_addr.ip4 = net_info->netifInfo.ipv4Info.ipv4Addr;
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int32_t ntp_callback(void *data, void *param)
|
||||
{
|
||||
sntp_result_t *result = (sntp_result_t *)data;
|
||||
DBG("%d,%d,%d", result->succ, result->sec, result->us);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void task_test_ntp(void *param)
|
||||
{
|
||||
uint8_t ntp_sleep_handler;
|
||||
slpManSetPmuSleepMode(true, SLP_HIB_STATE, false);
|
||||
slpManApplyPlatVoteHandle("ntp", &ntp_sleep_handler);
|
||||
slpManPlatVoteDisableSleep(ntp_sleep_handler, SLP_SLP2_STATE);
|
||||
|
||||
g_s_demo.wait_link_sem = xSemaphoreCreateBinary();
|
||||
|
||||
registerPSEventCallback(PS_GROUP_ALL_MASK, ps_callback);
|
||||
|
||||
xSemaphoreTake(g_s_demo.wait_link_sem, portMAX_DELAY);
|
||||
SntpInit("ntp1.aliyun.com", SNTP_DEFAULT_PORT, 1, g_s_demo.ipv4_cid, ntp_callback, NULL);
|
||||
while(1)
|
||||
{
|
||||
vTaskDelay(300000);
|
||||
if (!g_s_demo.is_link_up)
|
||||
{
|
||||
xSemaphoreTake(g_s_demo.wait_link_sem, portMAX_DELAY);
|
||||
}
|
||||
SntpInit("ntp1.aliyun.com", SNTP_DEFAULT_PORT, 1, g_s_demo.ipv4_cid, ntp_callback, NULL);
|
||||
}
|
||||
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
static void task_demo_ntp(void)
|
||||
{
|
||||
xTaskCreate(task_test_ntp, "ntp", 1024, NULL, 20, NULL);
|
||||
}
|
||||
//启动task_demoF_init，启动位置任务2级
|
||||
INIT_TASK_EXPORT(task_demo_ntp, "1");
|
||||
|
||||
@@ -0,0 +1,23 @@
|
||||
local TARGET_NAME = "example_ntp"
|
||||
local LIB_DIR = "$(buildir)/".. TARGET_NAME .. "/"
|
||||
local LIB_NAME = "lib" .. TARGET_NAME .. ".a "
|
||||
|
||||
target(TARGET_NAME)
|
||||
set_kind("static")
|
||||
set_targetdir(LIB_DIR)
|
||||
--使用第三方的ntp
|
||||
includes(SDK_TOP .. "/thirdparty/sntp")
|
||||
add_deps("sntp")
|
||||
--加入代码和头文件
|
||||
add_includedirs("/inc",{public = true})
|
||||
add_files("/src/*.c",{public = true})
|
||||
|
||||
--路径可以随便写,可以加任意路径的代码,下面代码等效上方代码
|
||||
-- add_includedirs(SDK_TOP .. "project/" .. TARGET_NAME .. "/inc",{public = true})
|
||||
-- add_files(SDK_TOP .. "project/" .. TARGET_NAME .. "/src/*.c",{public = true})
|
||||
|
||||
--可以继续增加add_includedirs和add_files
|
||||
--自动链接
|
||||
LIB_USER = LIB_USER .. SDK_TOP .. LIB_DIR .. LIB_NAME .. " "
|
||||
--甚至可以加入自己的库
|
||||
target_end()
|
||||
Reference in New Issue
Block a user